This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to the manufacture and testing of static random access memories (SRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
An example of a conventional SRAM cell is shown in FIG. 1a. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel MOS load transistor 3a and n-channel MOS driver transistor 4a, and the other inverter of series-connected p-channel MOS load transistor 3b and n-channel MOS transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel MOS pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel MOS pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
The body nodes of p-channel transistors 3a, 3b are typically connected to power supply voltage Vdda (by way of an n-well connection), and the body nodes of n-channel transistors 4a, 4b, 5a, 5b are typically connected to ground voltage Vssa (by way of a p-well connection). This condition, in which the voltage difference between the body nodes and source nodes of the transistors in memory cell 2 is zero, is commonly referred to as the “zero back-bias” or “normal back-bias” condition.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
One type of SRAM functional failure is referred to as a cell stability failure. In general, a cell stability failure occurs if noise of sufficient magnitude couples to the bit lines of unselected cells, for example during a write to a selected memory cell in the same row, to cause a false write of data to unselected cells in that same row. In effect, such write cycle noise can be of sufficient magnitude as to trip the inverters of one or more of the unselected cells (i.e., the “half-selected” cells in unselected columns of the selected row). The possibility of such a cell stability failure is exacerbated by device mismatch and variability, as discussed above.
Write failures are the converse of cell stability failures—while a cell stability failure occurs if a cell changes its state too easily, a write failure occurs if an addressed cell is stubborn to being written with the opposite data state. In general, write failures are due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, if cell 2 is storing a “1” state (its load transistor 3a on, and driver transistor 4a off), an attempt to write a low logic level to storage node SNT will fail if bit line BLTk is unable to sufficiently discharge storage node SNT to a sufficient level to trip the inverters. As such, SRAM write failures occur if the drive of the pass transistor is sufficiently weak, relative to the drive of the p-channel load transistor pulling up the storage node to be written.
Conventional manufacturing tests of SRAMs include various tests of the writeability of each memory cell. These writeability tests amount to the writing of both data states “0” and “1” over the previously stored opposite data states, followed by reads of the newly written data state, under one or more bias conditions intended to screen out those SRAM cells with weak “write margin”. Conventional write margin measurements include sweeping the low side bit line voltage above ground; sweeping the word line voltage below the power supply voltage Vdda; measuring the write current on the low side bit line; and characterizing the write noise margin corresponding to the well-known “butterfly” curve. Manufacturing test conditions are typically derived based on these measurements for each particular SRAM design, and can include some sort of “guardband” in which one or more of the relevant operating voltages is set at a harsher voltage than in normal operation (e.g., low side bit line voltage during write may be held at a selected voltage above ground), thus screening out those SRAM cells with weak write margin. Those weak cells may be replaced by conventional redundancy techniques, or the memory itself may be considered as failed.
Accelerated operating life test of certain integrated circuits have exhibited early life failures appearing as write failures to one or more SRAM cells. These SRAM cells had previously successfully passed the conventional write margin screening. Failure analysis indicated that many of these write failure cells exhibit manufacturing defects on the “bit line side” of the pass transistors, resulting in asymmetry in those cells. One particular type of defect causing such failures appeared as a missing lightly-doped drain extension on that side of the transistor; other manufacturing defects were similarly observed as causing such asymmetry.
FIG. 1b illustrates an example of the electrical effect of such a bit line side defect in an instance of SRAM cell 2. In this example, pass transistor 5a, coupled between storage node SNT and bit line BLTk exhibits this type of defect, for example as corresponding to a missing drain extension on the side of pass transistor 5a electrically closest to bit line BLTk. In that case, as in the case of other similarly-behaving defects, the conduction path between the channel of transistor 5a (when on) and bit line BLTk is more resistive than normal, as exhibited by resistor 5Rds in FIG. 1b. It has been observed, in connection with this invention, that the effective resistance of resistor 5Rds can be on the order of 10 to 50 kΩ. This resistance reduces the ability of bit line BLTk and pass transistor 5a to pull storage node SNT sufficiently low to trip the state of the cell.
Because of the bit line side location of this defect, conventional manufacturing “time zero” screens have not effectively screened out these marginal cells. However, it has been observed that even modest degradation of the cell transistors in accelerated operating life test (or burn-in, as the case may be) shifts the write performance enough to cause early life write failures in a number of devices. It is believed that the degradation mechanism resulting in these failures is channel hot carrier shifts.
By way of further background, conventional manufacturing test flows, for example as applied to solid-state SRAM arrays in wafer form, may include a static stress to accelerate early life defects. FIG. 1c illustrates an example of such a conventional test flow as applied to the SRAM array under test, beginning with process 10 in which conventional DC tests (e.g., leakage, power dissipation, etc.) are performed. Assuming the SRAM array meets the DC requirements, a checkerboard data pattern (i.e., alternating “0” and “1” data states) is selected in process 11, and is written into the SRAM array under test, with the power supply voltage Vdda applied to the memory cells set at a nominal level (e.g., 1.2 volts), in process 12. With the checkerboard pattern written into the SRAM array, power supply voltage Vdda as applied to the memory cells is increased to a stress level (e.g., 1.8 volts), in process 13. This stress bias level is applied to the memory cells in the SRAM array under test for a selected duration, in process 14; for example, this static stress duration may be on the order of three seconds. Following the static stress of process 14, power supply voltage Vdda is lowered to its nominal level in process 15. After this first stress with the checkerboard pattern written (as determined by decision 16 indicating “no”), an inverse checkerboard pattern (i.e., the opposite data state for each memory cell in the SRAM array under test, as compared with the checkerboard pattern) is selected in process 17, and written into the SRAM array at nominal Vdda in process 12. The SRAM array is again stressed with this inverse data pattern in processes 13 and 14.
After return to nominal bias in process 15 following the static stress applied in both data states (decision 16 indicating “yes”), a write screen test is performed on the SRAM array under test in process 18a, for example by way of one or more writeability tests under bias conditions intended to screen out those SRAM cells with weak “write margin”, perhaps including a “guardband” in which one or more of the relevant operating voltages is set at a harsher voltage than in normal operation (e.g., low side bit line voltage during write may be held at a selected voltage above ground). If the entire SRAM array under test passes the write screen test, as determined by pass/fail decision 18b, the device moves on to additional testing as desired. If one or a few (less than some limit n) memory cells in the SRAM array fail the write screen test after static stress, those weak cells may be replaced by conventional redundancy techniques and retested by way of the write screen test in process 19a; if decision 18b determines that more cells failed than can be repaired by redundancy, the SRAM array is considered to have failed. Decision 19b determines whether all memory cells in the SRAM array, following repair, have now passed the write screen test, and identifies the SRAM array as either passing or failing as a result.